How to make your life a little easier when designing electronics?
GALILEO by Intel®. Honestly taken from here (https://www.ema-eda.com/sites/ema/files/Constraint%20Management.zip) and maintenance of the developed electronic product.
There will be no secret knowledge or revelations. I will just describe a number of tricks that help save a little time on debugging and a little more of your own nerves. All this separately, obviously, can be found on the net in one form or another.
All of the following is by no means the ultimate truth, but just the private professional opinion of the author.
And further. If you recognize only EPSN-40, solid rosin and soldering fat, apply sealant sausages with your hands and trace in the sprintlayout, most likely some tips and ideas will not work for you, so feel free to skip them and do not waste your time and nerves on proving that that everything works anyway.
In fact, on any issue indicated below, you can write from a whole article to a monograph, I will try to limit myself to a reasonable minimum. An inquisitive reader will be able to continue research on topics of interest on his own.
Many hours later: while I was writing this article, I realized that everything with one sheet would probably be too tedious and it would still be worthwhile to break up a little what I wanted to tell.
Seats and 3D modelsWhat is the main pain of an electronics developer? Basically, even if you work according to the agile methodology (sprints, backlogs, etc.), all the same, all your processes are very stretched out in time and begin to resemble a waterfall in terms of the complexity of fixing problems. We will not consider the obvious problems with incorrect circuitry. Let's turn to the basic thing.
And what is such for printed circuit boards?
Correctly. ERI Seats!
First of all, forget about such a thing as someone else's footprints from an incomprehensible (or understandable) library from the Internet. Only your own, only hardcore! Yes, it is difficult, especially when electronic design is not your main field of activity. But if you want to make really high-quality electronics - start making footprints yourself. So they will contain your and only your mistakes, and not someone else's. It is not that difficult, especially if you use adequate generators. For example, the disadvantages of the free version of PCB Library Expert can be tolerated. But you get IPC boarding out of the box. Together with adequate three-measures. At the same time, when creating your ERI library, you better agree in advance on how the files will be named. It makes sense if you draw landing gears using IPC, and call them the same using the IPC methodology. After all, you are aware (huh?) That the same capacitors, the same dimensions in the plane, can have completely different heights, and sometimes this can be decisive.
RESC100X50X40L25N Why is it so important? Adherence to the IPC recommendations allows for guaranteed adequate soldering in most cases (for many standard housings). Because people tried, put their experience and knowledge into the information contained in IPC-7351B and other documents of this wonderful organization ( down with almost two and a half hours of time and my ears are slightly wilted from Robert's accent, but it's worth it, I recommend !). How many of my boards were soldered, whether by hand or on the conveyor in the reflow oven, there were practically no problems. At the same time, IPC landing gears are quite suitable for manual soldering. Maybe with the help of EPSN you don't solder them (in fact, it depends a lot on the tip), but with some T12 series clone - it's easy!
There is another common option: draw a footprint as recommended by the manufacturer. I do this if the case does not belong to any standard case and there is no adequate generator for it.
A typical example of a non-standard TI tryndet For the very lazy, there are services such as SnapEDA, Ultra Librarian and others that provide you with the services of generating footprints, UGO and three-dimensional ERIs of interest to you. Since these services are focused on mass export, as a rule, they do not take into account some features of specific electrical CAD systems. For example, in SnapEDA, it is not possible to issue landings with rounded corners. And it is still a pleasure to redo the landing pages generated from such services. If you take three-measures from there, be sure to check the dimensions. The same goes for 3D ContentCentral and GrabCAD. No matter how much I tried to use something from there unchanged, there were always discrepancies in size.
Solder mask (left) and contours imported from pdf (right) If an ERI manufacturer gives in the documentation a normal vector drawing of his product (you know how to distinguish a vector image in pdf from a raster one by eye?), It can be extremely useful to translate it into, for example, dxf , which later, as a rule, can be imported into your favorite CAD system to make sure that everything that you have drawn is true. This is an alternative paperless ( not as the wonderful Robert advises a) method for checking the adequacy of your footprint. In the comments to the video, they also suggest printing for verification not on paper, but on transparent film, but this is also something like that. What to do with statics? What if the components are still in procurement and will arrive in ten weeks? In general, it is debatable. By the way, when importing dxf, it is always good to check whether the spaced dimensions correspond to the real ones (and it's not just the wonderful words not to scale in the drawing from the documentation). I still have not figured out where the errors in the sizes imported from pdf come from, but it happens. So check, check and check again! For some reason, the expensive compass in the photo below did not work. I wonder why?
The real developer's cant (the wrong step of the pads is chosen) with the dimensions from my practice. And it was soldered. Alexander, if you recognize your design, do not be offended, please! And the old woman, as they say, Why bother with 3s in the library at all? It's very simple: to make it easier for yourself and your colleagues to design the hull and, in general, any related mechanics. It is much easier to immediately bind a model to a component when you create a component, than it is to strained to match the applied footprints with the existing models after routing the entire board. And again, do not be lazy to use specific three-dimensional models, and not a single conditional capacitor "0603" for the entire passive 0603. In addition, many manufacturers provide three-dimensional models of their products, which, among other things, can be used to control the adequacy of the creation of a footprint.
Almost all modern electrical CAD systems are able to generate three dimensions in one form or another. It can be useful to show it to the assembler before installation. Sometimes one glance at it is enough to understand some nuances.
SilkSome consider the following advice to be a collective farm, but personally I don't see anything collective farm in this: make different silk for resistors and capacitors. Of course, this applies to SMD components.
Can you guess where this power supply has the feedback resistors?
Not a perfect board, but it works Obviously, if there is no silk on the board, it won't help. Basically, this silk is useful when hand-soldering. It happens that the installer's eye gets blurry, and the installation sites get confused with each other. Or some people confuse capacitors and resistors (yes, there are such installers). At the stage of debugging prototypes, such marking greatly facilitates the initial diagnostics of the assembly.
Another silk tip - try to always and everywhere, if necessary, place an additional sign of the first conclusion. Whether it's a connector, a microcircuit or a transistor, labeling the first pin is always useful. Moreover, over the years I came to the conclusion that the most convenient symbol for this is an equilateral triangle, and not a point, plus sign or whatever is sometimes drawn there.
Silk triangles It is quite obvious from the photo, where the first pin is at the connectors and the transistor. What if they were just three dots? Well .... maybe it would be understandable, but silk is not always of good quality and sometimes an intentional point can be confused simply with a conditional blot.
opt3001What to do when there is no point in ordering silk, but you want to show the first output? It's simple. Transfer the triangle to the copper layer (or reveal mask). Of course, if the surrounding space allows. Another convenient technique when you plan to order silkscreen printing: draw on multi-legged connectors not only the first pin, but also with a certain step the numbers of other pins. When debugging a device, this makes it very easy to poke an oscilloscope, since you do not have to manually count any seventy-third pin from the beginning or count what it will be there in order from the end if you have 120 pins in the connector.
How it was designed and how it happened. Everything soldered is already in work, but the meaning is clear This is the UART connector. You can figure it out for yourself why the earth is in the center and not on the side? you practically don't need a wiring diagram. It will be enough just an electrical principle with signed contact numbers. What to do with through connectors? I am very upset by printed circuit boards, on which the first contact in the connectors is not marked in any way with copper that is different in shape. After all, it is immediately obvious where the first contact is. This can be very useful when debugging in the fields, when the board is installed in the case, you bent in the shape of a letter si with the oscilloscope probe and barely crawl to the connector, but the silk remained on the other side and you, highlighting yourself with a zippo, think - where is is the first pin in the connector? You will never get confused with this. By the way, I would be very grateful if someone in the comments explains to me the meaning of the oval-elongated eagle-style pads for the output connectors. I somehow still don't understand this.
Layer orderHow it was and how it was done It is quite clear that if you are making a double layer, then most likely gerberas (I really hope that you are giving gerberas to production, not projects) have names for copper like TOP \ BOT or Top \ Bottom and the like. And how to make sure that the technologist has read your note about the order in which copper goes? Or that the layers are not trivially mixed up? I have had this several times. Thanks to the method described below, the plant recognized the defect without any problems and delays and reworked everything at its own expense. The trick is simple and effective. Add layer numbers directly to copper. Here's another example on the left. The top shows how it is designed, and then the top and bottom views. Do not forget to open the mask at the location of such markings. Use a flashlight to see through if necessary. Yes, of course, it all depends on the thickness of the dielectric layers, but, as a rule, everything is clearly visible on four layers. On six-ply, just with numbers, everything is already much worse. What to do in this case? Ladder. Like this:
Copper ladder (https://dornerworks.com/blog/pcb-stacking-stripes-could-change-the-way-you-look-at-hardware) And this is how it looks on a real board:
PCB end view (https://resources.altium.com/p/pcb-design-test-test-structures-and-types-tests-part-1) Altium blog article and to look video from another article ... I myself have not made such ladders yet, because basically everything I do is two-layer and four-layer. The obvious disadvantage of such ladders is that many manufacturers really do not like to mill copper with that cutter (it’s dull, you see, and the scuffs remain), which gnaw out the circuit board outline. And they write separately that there must be a certain minimum distance between the milled contour and the nearest copper. But, I suppose, if you draw the attention of the technologist to the fact that the project is so specially laid down, no one will particularly object.
Engineers from Gigabyte (http://www.xtremesystems.org/forums/showthread.php?267340-Sandybridge-for-overclocking-two-solutions-review) approve. I saw the same markings on some Asus motherboards.
AlignmentAlthough editing itself is a completely separate topic, it is worth mentioning a thing that can make it a little easier.
In an ideal world, there is a circuit designer, topologist, SI, PI and many other engineers who should work on a project in an amicable way. But, life often makes its own adjustments, and sometimes you have to do it yourself (yes, the collective farm as it is!). And when there are ERIs in the project, which, due to the size, weight or soldering technology, will not be able to self-center normally guaranteed due to the surface tension of the solder, I want to initially set them as accurately as possible. It's good when there is a special manipulator for installing components. And what to do when there are only tweezers, and even those are not vacuum ones at all?
And there is such a technique:
Opening the mask in the corners under the body (left), it is with the body's perimeter (center), as it looks in orthographic projection in 3D (right) The idea is very simple: in the corners of the component we open the solder mask (if the surrounding topology allows it, obviously). An opening line width of 0.15mm is sufficient. Since the alignment accuracy of the mask layers with copper in the production of a printed circuit board is significantly better than the alignment accuracy of copper and silk, it can be hoped that the exposed corners will be in place. With silk, this sometimes does not work, especially on multi-row BGA cases, when I shifted everything by 0.5 mm and already missed a whole row. Obviously, you need to understand for what so-called. material condition you make your models and footprints, for nominal or maximum (I do everything for nominal) and, accordingly, you can expect that the corners will not always work perfectly.
In real life it looks like this. My microscope does not orthographic projection (weird huh?), So only one angle is shown How to work with this in reality? It's very simple. You applied the paste through the stencil (don't skimp on the stencil, by the way!) And start placing the components. Instead of immediately lowering and pressing the component onto the paste from one go, gently lower it onto the surface of the paste and, looking from the corners, achieve maximum symmetry of the arrangement. And only after that, press the component against the paste, also not zealous, so as not to move. As a rule, if the paste of the third type is not expired and has not been baked with a homemade flux, the suspension will very slightly stain the component pads. If necessary, before pressing, you can even remove the component and not transfer the paste or clean the component pads.
Last but not leastOtherwise it will be like this https://www.eevblog.com/forum/projects/silk-screen-on-exposed-pcb-pads Check the gerberas that you send to the plant, do not be lazy! I will not recommend specific software here, since there are many different viewers with different complexity of use and tasks that they can solve. It is better if you look at gerberas in a different program that generates them. Well, just in case. Probably very cool if you can measure something in such a viewer (the same minimum clearances and thicknesses, for example, to make sure that your board meets a certain accuracy class). Verification of gerberas, even purely visually, helps to avoid stupid mistakes. You are an engineer who designs a printed circuit board. In general, a plant technologist is not obliged to think for you. His task is to make you a board as close as possible to what you sent. And what you designed there is not his concern. Maybe you need it that way.
Hope it didn't get too boring and you could learn something useful.
The rest of the chips that I try to use, I will try to tell you next time.
Stay tuned, as they say!
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